A programmable logic device ("PLD") typically includes an array of programmable elements forming programmable interconnections of signal lines. The programmable elements typically include memory cells such as nonvolatile erasable programmable read only memory ("EPROM") cells, electrically erasable programmable read only memory ("EEPROM") cells, and flash memory cells.
The array of programmable memory cells is tyically organized into a number of rows and columns. Each column or row may have a sense amplifier to sense the state of one or more selected memory cells. For example, FIG. 1 shows a conventional sense amplifier 100 for sensing the state of memory cell 102. Memory cell 102 has a drain coupled to a bit line 104, a source coupled to source line 106, and a select gate coupled to word line 108. Memory cell 102 may be selected for reading by activating word line 108.
A state stored by memory cell 102 may be sensed by sense amplifier 100 as follows. When memory cell 102 is "OFF" (i.e., either programmed or erased depending on the technology), it typically does not provide a conduction path between lines 104 and 106 when word line 108 is activated. The voltage difference maintained between lines 104 and 106 is sufficiently large to turn on transistors 112 and 118 such that node 114 is pulled low. This causes the output of sense amplifier 100 to be high on line 110. When memory cell 102 is "ON" (i.e., either or programmed or erased depending on the technology), it typically provides a conduction path between lines 104 and 106 when word line 108 is activated. The voltage difference on lines 104 and 106 will drop to less than the threshold voltage of transistor 112 causing node 114 to be pulled high and sense amplifier 100 to output a low state on line 110.
The difference in the potential between line 104 and 106 at which sense amplifier 100 can sense a transition of a state of memory cell 102 is generally referred to as the trip point or trip voltage for sense amplifier 100. The speed of sense amplifier 100 is related to how close the voltage difference between lines 104 and 106 is to the trip point. Therefore, one method of increasing the speed or switching time of sense amplifier 100 is to limit the voltage difference between 104 and 106. U.S. Pat. No. 5,525,917 discloses feedback circuitry that limits the voltage swing on lines 104 and 106 to improve the switching speed of a sense amplifier such as sense amplifier 100.
The speed of sense amplifier 100 is also related to the slew rate of the signal at node 114 as it transitions from a high state to a low state or from a low state to a high state. The slew rate of the output signal on line 110 will generally follow the slew rate of the signal at node 114. Therefore, if the slew rate of the signal at node 114 is increased as it transitions from one state to another, the slew rate of the signal on line 110 may similarly increase. Therefore, it is desirable to increase the switching speed of a sense amplifier by increasing the slew rate of a transition of the signal at node 114 and the slew rate of a transition of the output signal at output line 110.